Semiconductor test system and method
US-9222977-B2 · Dec 29, 2015 · US
Addressable tap domain selection circuit with AUXI/O, TDI/TDO, TMS/TRCK leads
US8938652B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8938652-B2 |
| Application number | US-201313941732-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 15, 2013 |
| Priority date | Nov 4, 2004 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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Abstract
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This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41 - 49 , provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: A. plural TAP domains, each domain having a TDI input terminal, a TDO output terminal, a TCK input terminal, a TMS input terminal, and a RCK output terminal; and B. an addressable TAP domain selection circuit, the selection circuit having a separate set of outputs and at least one input for each TAP domain, each set including a TDI output connected to a TDI input terminal, a TDO input connected to a TDO output terminal, a…
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- G01R31/318541Primary
Physics · mapped topic
- G01R31/3177Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8938652B2 cover?
- This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, d…
- Who is the assignee on this patent?
- Texas Instruments Inc
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318541. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).