Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US8938575B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8938575-B2 |
| Application number | US-201213438438-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 3, 2012 |
| Priority date | Apr 3, 2012 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells.
Opening claim text (preview).
We claim: 1. A multi-state memory system with minimized half-select currents, the system comprising: a plurality of arrays of row conductors and column conductors; a plurality of storage cells each capable of being placed into any of three or more physical states, each storage cell connected between a different combination of a row conductor and a column conductor; and an encoder connected to receive data bits for storage and to apply activation signals m the row conductors and…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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