Memory device redundancy management system

Patent metadata

Field	Value
Publication number	US-8937845-B2
Application number	US-201213665917-A
Country	US
Kind code	B2
Filing date	Oct 31, 2012
Priority date	Oct 31, 2012
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.

First claim

What is claimed is:

1. A system for managing redundancy in a memory device, wherein the memory device includes a first memory array and a first periphery logic circuit associated therewith, and at least one redundant memory array and a redundant periphery logic circuit associated therewith, wherein the first periphery logic circuit includes first and second logic circuits, and wherein the second logic circuit includes first and second sets of logic circuits, the system comprising:…

Assignees

• Freescale Semiconductor Inc

Inventors

• Verma Chetan
• Mishra Piyush Kumar
• Sharma Ashish

Classifications

• G11C29/4401 Primary

  Physics · mapped topic

• G11C29/848

  Physics · mapped topic