Memory module including memory devices to which unit id is assigned and storage device including the same
US-2024345944-A1 · Oct 17, 2024 · US
Data paths using a first signal to capture data and a second signal to output data and methods for providing data
US8937839B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8937839-B2 |
| Application number | US-201414259403-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 23, 2014 |
| Priority date | Nov 2, 2010 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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Abstract
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Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
First claim
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What is claimed is: 1. An apparatus comprising: a clock path configured to delay a clock signal approximately a same amount as a data signal is delayed in a data path; and a data register coupled to the clock path and the data path and configured to capture data based on the delayed clock signal and provide the data based on the clock signal. 2. The apparatus of claim I, wherein the delayed clock signal is delayed in relation to the clock signal.…
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- What does patent US8937839B2 cover?
- Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the cloc…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C7/10. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).