Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
US8937511B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8937511-B2 |
| Application number | US-201213681737-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 20, 2012 |
| Priority date | Nov 22, 2011 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
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What is claimed is: 1. A system comprising: a plurality of amplifiers configured to generate a clock signal having a frequency, wherein the clock signal is input to a processor, wherein the amplifiers are connected in series, wherein an output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers, and wherein each of the amplifiers has a transconductance; and a frequency adjustment module configured to adjust, based on an activity le…
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