Delay method, circuit and integrated circuit

Patent metadata

Field	Value
Publication number	US-8937500-B2
Application number	US-201314109161-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2012
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.

First claim

What is claimed is:

1. A delay circuit, comprising:
an oscillator configured to supply clock signals;
a first register configured to be written with a delay reference code;
a second register configured to be written with a delay factor;
a storage unit configured to store delay factors and corresponding delay ratios;
a control unit configured to determine a corresponding delay ratio in the storage unit based on the delay factor in the second register; and
a first digital…

Assignees

• Fairchild Semiconductor

Inventors

• Lam Ming Chuen Alvan
• Sun Weiming
• Wang Emma
• Zhu Peng

Classifications

• H03K5/14 Primary

  Electricity · mapped topic