Semiconductor package, method and mold for producing same, input and output terminals of semiconductor package

US8937374B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8937374-B2
Application numberUS-201214003816-A
CountryUS
Kind codeB2
Filing dateOct 24, 2012
Priority dateDec 22, 2011
Publication dateJan 20, 2015
Grant dateJan 20, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having another end exposed from the resin; and a ground enhancing metal body encapsulated in the encapsulation resin, having a first main surface facing the lead terminal and a second main surface exposed from the encapsulation resin, wherein the ground enhancing metal body has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor package comprising: a semiconductor element where a high frequency signal is input and/or output; a planar lead for transmitting the high frequency signal to the semiconductor element or an external circuit, the lead having an end electrically connected to an input terminal or an output terminal of the semiconductor element; a resin for encapsulating the lead and the semiconductor element, the lead having another end exposed from th…

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What does patent US8937374B2 cover?
A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having anothe…
Who is the assignee on this patent?
Panasonic Corp
What technology area does this patent fall under?
Primary CPC classification H10W74/121. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).