Contact formation for ultra-scaled devices

Patent metadata

Field	Value
Publication number	US-8937359-B2
Application number	US-201313894513-A
Country	US
Kind code	B2
Filing date	May 15, 2013
Priority date	May 15, 2013
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

First claim

What is claimed is:

1. A method of forming a device, the method comprising:
forming a gate transistor over a substrate;
forming a source/drain (S/D) contact over a trench-silicide (TS) layer formed adjacent the gate transistor; and
forming a gate contact over the gate transistor, wherein at least a portion of the gate contact is positioned over the TS layer.

2. The method according to claim 1 , further comprising forming a set of fins in an active region…

Assignees

• Globalfoundries Inc
• IBM

Inventors

• Xie Ruilong
• Ponoth Shom
• Horak David V
• Pranatharthiharan Balasubramanian

Classifications

• H10W20/076

  Electricity · mapped topic

• H10W20/069

  Electricity · mapped topic

• H10W20/056

  Electricity · mapped topic

• H10W20/075

  Electricity · mapped topic

• H10W20/077 Primary

  Electricity · mapped topic