Backside contacts for semiconductor devices
US-2024371700-A1 · Nov 7, 2024 · US
Striped on-chip inductor
US8937355B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8937355-B2 |
| Application number | US-201213469464-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 11, 2012 |
| Priority date | Sep 29, 2006 |
| Publication date | Jan 20, 2015 |
| Grant date | Jan 20, 2015 |
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Abstract
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Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
First claim
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What is claimed is: 1. A sub-100 nanometer process semiconductor inductor comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and connecting a first inductor port to a second inductor port; the lines each having a width and a cross-sectional area, each line spaced from an adjacent line by a spacing gap; wherein the plurality of line widths, cross-sectional areas and spacing gaps are a function of Design Rule Check rules comprising a Chemical Me…
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- What does patent US8937355B2 cover?
- Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density rat…
- Who is the assignee on this patent?
- Cho Choongyeun, Kim Daeik, Kim Jonghae, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D89/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).