Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-8936965-B2
Application number	US-201113295469-A
Country	US
Kind code	B2
Filing date	Nov 14, 2011
Priority date	Nov 26, 2010
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

A normally-off transistor having an oxide semiconductor layer in a channel formation layer is provided. The transistor comprises: a first oxide semiconductor layer functioning as a channel formation region; a source electrode layer and a drain electrode layer which overlap with the first oxide semiconductor layer; a gate insulating layer which is provided over and in contact with the first oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a second oxide semiconductor layer which is provided over and in contact with the gate insulating layer and overlaps with the first oxide semiconductor layer; and a gate electrode layer provided over the second oxide semiconductor layer. A manufacturing method thereof is also disclosed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first oxide semiconductor layer over a substrate;
a source electrode layer and a drain electrode layer over the first oxide semiconductor layer;
a gate insulating layer over and in contact with the first oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
a second oxide semiconductor layer over and in contact with the gate insulating layer, the second oxide semiconductor layer comprising gallium and indium; and
a gate electrode layer over and in contact with the second oxide semiconductor layer, the gate electrode layer comprising a metal selected from molybdenum, titanium, tantalum, tungsten, aluminum, and copper,
wherein the gate electrode layer covers the second oxide semiconductor layer so that a side surface of the second oxide semiconductor layer is in direct contact with the gate electrode layer.

2. The semiconductor device according to claim 1 , wherein a work function of the second oxide semiconductor layer is greater than or equal to 4 eV and less than 5 eV.

3. The semiconductor device according to claim 1 , further comprising an oxide insulating film between the substrate and the first oxide semiconductor layer.

4. The semiconductor device according to claim 3 , wherein the oxide insulating film includes oxygen which exceeds a stoichiometric proportion.

5. The semiconductor device according to claim 1 , wherein the gate electrode layer comprises aluminum.

6. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer is an In—Ga—Zn—O film.

7. The semiconductor device according to claim 1 , wherein the gate insulating layer comprises gallium.

8. A method for manufacturing a semiconductor device comprising the steps of:
forming a first oxide semiconductor layer over a substrate;
forming a source electrode layer and a drain electrode layer over and in contact with the first oxide semiconductor layer;
forming a gate insulating layer over and in contact with the first oxide semiconductor layer, the source electrode layer, and the drain electrode layer;
forming a second oxide semiconductor layer over and in contact with the gate insulating layer, the second oxide semiconductor layer comprising gallium and indium; and
forming a gate electrode layer over and in contact with the second oxide semiconductor layer, the gate electrode layer comprising a metal selected from molybdenum, titanium, tantalum, tungsten, aluminum, and copper,
wherein the gate electrode layer covers the second oxide semiconductor layer so that a side surface of the second oxide semiconductor layer is in direct contact with the gate electrode layer.

9. The method according to claim 8 , wherein a work function of the second oxide semiconductor layer is greater than or equal to 4 eV and less than 5 eV.

10. The method according to claim 8 , further comprising a step of forming an oxide insulating film between the substrate and the first oxide semiconductor layer.

11. The method according to claim 10 , wherein the oxide insulating film includes oxygen which exceeds a stoichiometric proportion.

12. The method according to claim 8 , wherein the gate electrode layer comprises aluminum.

13. The method according to claim 8 , wherein the second oxide semiconductor layer is an In—Ga—Zn—O film.

14. The method according to claim 8 , wherein the gate insulating layer comprises gallium.

Assignees

• Imoto Yuki
• Asano Yuji
• Maruyama Tetsunori
• Semiconductor Energy Lab

Inventors

• Imoto Yuki
• Asano Yuji
• Maruyama Tetsunori

Classifications

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title