Reconfigurable logic block

Patent metadata

Field	Value
Publication number	US-8935645-B2
Application number	US-201314048888-A
Country	US
Kind code	B2
Filing date	Oct 8, 2013
Priority date	Jul 1, 2011
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

First claim

What is claimed is:

1. A device comprising:
a logic block, wherein the logic block includes a plurality of logic elements;
configuration logic associated with the logic block, wherein the configuration logic is operable to identify values stored in the plurality of logic elements, and wherein the configuration logic includes a first group of configuration cells in an array;
a first memory cell storing a first mode flag value, wherein the mode flag value is operable to identify…

Assignees

• Altera Corp

Inventors

• Mendel David W
• Lai Gary
• Zhou Lu
• Pedersen Bruce B

Classifications

• G06F30/34 Primary

  Physics · mapped topic

• G06F11/1008

  Physics · mapped topic

• H03K19/17758

  Electricity · mapped topic

• H03K19/17756 Primary

  Electricity · mapped topic

• G06F17/5054 Primary

  Physics · mapped topic