Forward error correction with turbo/non-turbo switching
US-2015326253-A1 · Nov 12, 2015 · US
LDPC erasure decoding for flash memories
US8935595B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935595-B2 |
| Application number | US-201113583617-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 11, 2011 |
| Priority date | Mar 12, 2010 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: requesting, in response to receiving a request for data stored at a particular location in a flash memory, one or more initial reads at the particular location; detecting, in response to completing the initial reads, an uncorrectable error via a hard-decision based Low Density Parity Check (LDPC) decoding based on results of the initial reads; requesting, in response to the detecting, one or more additional reads at the particular lo…
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Classifications
Physics · mapped topic
Electricity · mapped topic
- H03M13/3715Primary
Electricity · mapped topic
- G06F11/1008Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8935595B2 cover?
- A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the S…
- Who is the assignee on this patent?
- Zhong Hao, Li Yan, Danilak Radoslav, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H03M13/3715. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).