Data processing method based on blockchain network and related product
US-2024419537-A1 · Dec 19, 2024 · US
US8935592B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935592-B2 |
| Application number | US-201213681789-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 20, 2012 |
| Priority date | Nov 20, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.
Opening claim text (preview).
We claim: 1. An apparatus comprising: a memory device comprising multiple memory regions, and configured to store data symbols and associated error correction code (ECC) symbols; read circuitry configured to perform a read operation in order to output a plurality of read symbols from said memory device, said read symbols comprising n data symbols and an associated m error correction code symbols, and comprising more than one read symbol from each memory region, both n and m bein…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.