Built-in self test circuit for measuring performance of clock data recovery and system-on-chip including the same
US-2024302432-A1 · Sep 12, 2024 · US
US8935586B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935586-B2 |
| Application number | US-201213671605-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 8, 2012 |
| Priority date | Nov 8, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.
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What is claimed is: 1. An integrated circuit structure comprising: a test controller; built-in self-test (BIST) controllers operatively connected to said test controller; and BIST engines operatively connected to said BIST controllers, said BIST engines being grouped into BIST domains, each BIST controller of said BIST controllers being connected to a single BIST domain of said BIST domains, each said BIST controller comprising: a register containing a BIST controller-speci…
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