Semiconductor integrated circuit and method for operating same
US-9367438-B2 · Jun 14, 2016 · US
Control computer system, method for controlling a control computer system, and use of a control computer system
US8935569B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935569-B2 |
| Application number | US-201113636091-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 18, 2011 |
| Priority date | Mar 23, 2010 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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- Title
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Abstract
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A control computer system comprising at least two modules ( 1, 2, 1001, 1002, 1003, 1004, 1021, 1071 ) which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit ( 20, 21, 91, 92, 1011, 1012 ) for monitoring the synchronization state of the at least two redundant modules ( 1, 2, 1001, 1002, 1003, 1004, 1021, 1071 ) and for detecting a synchronization error at least one peripheral unit ( 95, 96, 1022, 1030, 1031, . . . , 1038 ). At least one switching matrix ( 21, 1013, 1063 ) which is set up to allow or block access to the at least two redundant modules or access to the peripheral unit ( 95, 96, 1022, 1030, 1031, . . . , 1038 ) by the at least two redundant modules, and an error-handling unit ( 44, 1080 ) which is set up to receive signals from the at least one comparison unit ( 20, 21, 91, 92, 1011, 1012 ) and to drive the at least one switching matrix ( 1013, 1063 ) in order to completely or selectively prevent access to the at least two redundant modules or access to the peripheral unit by the at least two redundant modules.
First claim
Opening claim text (preview).
The invention claimed is: 1. A control computer system comprising: at least two processor pairs, each processing pair comprising at least two processors or cores which are designed to be redundant with respect to one another; at least two comparison units for monitoring the synchronization state of the at least two processors or cores of each processor pair and for detecting a synchronization error; at least one peripheral unit; at least one switching matrix which is set up…
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Physics · mapped topic
Physics · mapped topic
- G06F11/1641Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8935569B2 cover?
- A control computer system comprising at least two modules ( 1, 2, 1001, 1002, 1003, 1004, 1021, 1071 ) which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit ( 20, 21, 91, 92, 1011, 1012 ) for monitoring the synchronization state of the at least two redundant modules ( 1, 2, 1001, 1002, 1003, 1004, 1021, 1071 ) and for det…
- Who is the assignee on this patent?
- Kabulepa Lukusa Didier, Ehrenberg Thorsten, Baumeister Daniel, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F11/1641. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).