Architecture for managing asynchronous resets in a system-on-a-chip
US-2024192745-A1 · Jun 13, 2024 · US
US8935545B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935545-B2 |
| Application number | US-201213477061-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2012 |
| Priority date | May 26, 2011 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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A power generator adaptive to a computer apparatus is provided. The power generator includes a logic operating unit, a power converting module, and a power management module. The logic operating unit receives a power pulse signal generated by a power button when the power button is pressed. The logic operating unit generates a power enabling signal according to the power pulse signal. The power converting module receives the power enabling signal and generates an internal voltage by converting an external voltage according to the power enabling signal. The power management module receives the internal voltage and the power pulse signal, and latches a generating state of the internal voltage according to the power pulse signal to generate a power stable signal. The power management module further provides the power stable signal to the logic operating unit to maintain a generating state of the power enabling signal.
Opening claim text (preview).
What is claimed is: 1. A power generator, adaptive to a computer apparatus, comprising: a logic operating unit, receiving a power pulse signal generated by a power button, and generating a power enabling signal according to the power pulse signal; a power converting module, coupled to the logic operating unit, and receiving the power enabling signal and generating an internal voltage by converting an external voltage according to the power enabling signal; and a power manageme…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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