Adaptively time-multiplexing memory references from multiple processor cores

Patent metadata

Field	Value
Publication number	US-8935489-B2
Application number	US-201013500067-A
Country	US
Kind code	B2
Filing date	Nov 10, 2010
Priority date	Jan 19, 2010
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

First claim

What is claimed is:

1. A method for processing memory references in a system which includes multiple processor cores, the method comprising:
receiving a first plurality of memory references from a first processor core;
receiving, interleaved with said first plurality of memory references, a second plurality of memory references from at least a second processor core, each of said first plurality of memory references and said second plurality of memory references causing, in a giv…

Assignees

• Woo Steven C
• Diep Trung A
• Ching Michael T
• Rambus Inc

Inventors

• Woo Steven C
• Diep Trung A
• Ching Michael T

Classifications

• G06F13/1652 Primary

  Physics · mapped topic

• G06F9/52

  Physics · mapped topic

• Y02D10/00

  Cross-Sectional Technologies · mapped topic

• G06F9/5016

  Physics · mapped topic