Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US8935461B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935461-B2 |
| Application number | US-201313740948-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 14, 2013 |
| Priority date | Jul 20, 2010 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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A memory includes a storage element which stores the number of times of application of a rewrite voltage pulse into a memory array, and a required-time output unit which outputs data representing a required time for a rewrite operation based on the number of times of application stored in the storage element.
Opening claim text (preview).
What is claimed is: 1. A memory unit having a memory array having a plurality of memory cells which each store one of at least two values including a first value and a second value, where the memory unit performs a rewrite operation by repeating application of a rewrite voltage pulse and verification, comprising: a storage element configured to store a number of times of the application of the rewrite voltage pulse into the memory array; and a required-time output unit configure…
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