Apparatus and method for identifying a cause of an error occurring in a network connecting devices within an information processing apparatus
US-2015370683-A1 · Dec 24, 2015 · US
Network card detecting circuit
US8935451B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8935451-B2 |
| Application number | US-201213401968-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 22, 2012 |
| Priority date | Dec 22, 2011 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A detecting circuit includes a network interface, a switch, a baseboard management controller (BMC) having first and second signal pins, and a detecting unit. The first and second signal pins receive low level signals when the network line is disconnected from the network interface. The first signal pin receives a high level signal and the second signal pin receives a low level signal when the network line is connected to the network interface but the network card is malfunctioning. The first and second signal pins receive high level signals when the network line is connected to the network interface and the network card works normally.
First claim
Opening claim text (preview).
What is claimed is: 1. A network card detecting circuit applicable to a motherboard of a computer, the detecting circuit comprising: a resistor; a network interface; a switch arranged inside the network interface and comprising a first end connected to a direct current (DC) power and a second end grounded through the resistor; a detecting unit connected to first and second signal pins of a network card arranged on the motherboard, wherein the first and second signal pins of…
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- G06F11/2289Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8935451B2 cover?
- A detecting circuit includes a network interface, a switch, a baseboard management controller (BMC) having first and second signal pins, and a detecting unit. The first and second signal pins receive low level signals when the network line is disconnected from the network interface. The first signal pin receives a high level signal and the second signal pin receives a low level signal when the …
- Who is the assignee on this patent?
- Gao Zheng-Xin, Scienbizip Consulting Shenzhen Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F11/2289. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).