Feature layers for rendering of design options
US-2024013452-A1 · Jan 11, 2024 · US
Dividing work among multiple graphics pipelines using a super-tiling technique
US8933945B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933945-B2 |
| Application number | US-45979703-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 12, 2003 |
| Priority date | Nov 27, 2002 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.
First claim
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What is claimed is: 1. A graphics processing circuit, comprising: at least two graphics pipelines on a same chip operative to process data in a corresponding set of tiles of a repeating tile pattern corresponding to screen locations, a respective one of the at least two graphics pipelines operative to process data in a dedicated tile; and a memory controller on the chip in communication with the at least two graphics pipelines, operative to transfer pixel data between each of a…
Assignees
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- G06T11/40Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8933945B2 cover?
- A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes recei…
- Who is the assignee on this patent?
- Leather Mark M, Demers Eric, Ati Technologies Ulc
- What technology area does this patent fall under?
- Primary CPC classification G06T11/40. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).