Semiconductor device and method for manufacturing the same
US-2024363493-A1 · Oct 31, 2024 · US
Semiconductor chip package including voltage generation circuit with reduced power noise
US8933747B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933747-B2 |
| Application number | US-201213617802-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 14, 2012 |
| Priority date | Oct 10, 2011 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor chip package comprising: an integrated circuit chip including a voltage generation circuit that receives an external voltage to generate a supply voltage greater than the external voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit; and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of th…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10W44/601Primary
Electricity · mapped topic
- H01L23/642Primary
Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8933747B2 cover?
- A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circ…
- Who is the assignee on this patent?
- Kang Sunwon, Kim Chiwook, Woo hyun jeong, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W44/601. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).