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US-11977407-B2 · May 7, 2024 · US
Semi-dynamic flip-flop
US8933740B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933740-B2 |
| Application number | US-201414222914-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 24, 2014 |
| Priority date | Apr 10, 2013 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A semi-dynamic flip-flop is provided. A selecting circuit selects an input signal from a data signal and a test signal. A charging/discharging circuit charges/discharges an intermediate node according to the input signal, a clock signal and a modulation signal. A first storage circuit stores electric potential of the intermediate node. An adjusting circuit generates an adjustment signal according to the clock signal and the potential of the intermediate node. An output signal adjusts electric potential of an output node according to the clock signal and the potential of the intermediate node. A second storage circuit stores the potential of the output node. A reset circuit sets or resets the potential of the output node. A switch, connected between the adjusting circuit and the charging/discharging circuit, is turned on when the semi-dynamic flip-flop is in a normal operation mode.
First claim
Opening claim text (preview).
What is claimed is: 1. A semi-dynamic flip-flop, comprising: a selecting circuit, configured to select an input signal from a data signal and a test signal according to a selection signal; a charging/discharging circuit, connected to an intermediate node, configured to charge or discharge the intermediate node according to the input signal, a clock signal and an adjustment signal; a first storage circuit, connected to the intermediate node, configured to store potential of the…
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Classifications
- H03K3/356Primary
Electricity · mapped topic
- H03K3/356191Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8933740B2 cover?
- A semi-dynamic flip-flop is provided. A selecting circuit selects an input signal from a data signal and a test signal. A charging/discharging circuit charges/discharges an intermediate node according to the input signal, a clock signal and a modulation signal. A first storage circuit stores electric potential of the intermediate node. An adjusting circuit generates an adjustment signal accordi…
- Who is the assignee on this patent?
- Mstar Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification H03K3/356. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).