Delay-locked loop (DLL) circuit apparatus and method for locking thereof

Patent metadata

Field	Value
Publication number	US-8933736-B2
Application number	US-201414247672-A
Country	US
Kind code	B2
Filing date	Apr 8, 2014
Priority date	May 22, 2013
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A DLL circuit apparatus and a DLL locking method are provided. A control signal voltage value corresponding to a DLL locking state is stored, and a DLL unlocking state is detected when a change in control signal voltage value or a phase difference of clock signals occurs. When the DLL unlocking occurs, the DLL is locked again using the stored control signal voltage value. Accordingly, DLL unlocking from DLL locking state is quickly detected, and a fast DLL locking time occurs.

First claim

What is claimed is:

1. A delay-locked loop (DLL) circuit apparatus comprising:
a storage configured to store a control signal voltage value corresponding to a DLL locking state as a reference voltage value;
a lock detector configured to determine when a DLL unlocking state occurs using an external clock signal and a feedback internal clock signal;
a level determiner configured to determine when a DLL unlocking state occurs using a level of a control signal voltage value; and…

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Kim Jung Hyun

Classifications

• H03L7/0802 Primary

  Electricity · mapped topic

• H03L7/081 Primary

  Electricity · mapped topic

• H03L7/095

  Electricity · mapped topic

• G11C7/222

  Physics · mapped topic

• H03L7/1072

  Electricity · mapped topic