Clock generation circuit

Patent metadata

Field	Value
Publication number	US-8933735-B2
Application number	US-201214232257-A
Country	US
Kind code	B2
Filing date	Jul 12, 2012
Priority date	Jul 15, 2011
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signal as synchronized clock signal, and wherein the control circuit is adapted to toggle between the n delay locked loop circuits, in a way that the phase of the internal clock signal is successively shifted according to the current phase shift between the internal clock signal and the reference clock signal.

First claim

The invention claimed is:

1. A method of operating a clock signal generator circuit including at least a first and a second delay locked loop circuit, to respective inputs of which a locally generated clock signal is provided, each of the at least first and second delay locked loop circuits providing an output signal that is phase-shifted with respect to its input signal, the outputs of the at least first and second delay locked loop circuits being provided to respective inputs of…

Assignees

• Kropp Holger
• Schuetze Herbert
• Abeling Stefan
• Thomson Licensing

Inventors

• Kropp Holger
• Schuetze Herbert
• Abeling Stefan

Classifications

• H03L7/0814

  Electricity · mapped topic

• H03L7/22 Primary

  Electricity · mapped topic