Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Thermal via for 3D integrated circuits structures
US8933540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933540-B2 |
| Application number | US-201313780033-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 28, 2013 |
| Priority date | Feb 28, 2013 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
Official abstract text for this publication.
A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.
First claim
Opening claim text (preview).
What is claimed is: 1. A three dimensional (3D) integrated circuit structure comprising: a first chip having a first dielectric layer, a first plurality of through substrate vias (TSVs) and a first plurality of pads on the first dielectric layer, the first dielectric layer formed on a bottom surface of the first chip, the pads are electrically connected to the corresponding TSVs of the first chip; a second chip having a second dielectric layer, a second plurality of TSVs, and a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8933540B2 cover?
- A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. Th…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).