Memory with isolation structure

Patent metadata

Field	Value
Publication number	US-8933508-B2
Application number	US-201313799084-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Jun 24, 2005
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate having a doping concentration;
a memory cell comprising a charge storage device and a recessed access device, wherein the recessed access device extends into the substrate and is configured to induce a first depletion region in the substrate; and
an isolation structure configured to isolate the memory cell from an adjacent memory cell, wherein the apparatus is configured such that during operation the isolation struct…

Assignees

• Micron Technology Inc

Inventors

• Juengling Werner

Classifications

• H10B12/053

  Electricity · mapped topic

• H10B12/34 Primary

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L27/10823 Primary

  Electricity · mapped topic

• H10W10/051

  Electricity · mapped topic