Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Array substrate and display device comprising the same
US8933472B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933472-B2 |
| Application number | US-201313996318-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 9, 2013 |
| Priority date | Jan 12, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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An array substrate, which is formed with a gate electrode ( 2 ), a source electrode ( 5 ), a drain electrode ( 6 ), a gate insulating layer ( 3 ), an active layer ( 4 ) and a passivation layer ( 9 ) in a thin film transistor region, and with the gate insulating layer ( 3 ), a pixel electrode ( 7 ), the passivation layer ( 9 ) and a common electrode ( 8 ) in a pixel electrode pattern region, and a color resin layer ( 11 ) is formed between the passivation layer ( 9 ) and the common electrode ( 8 ). Since the color resin layer ( 11 ) for planarization is formed on the passivation layer ( 9 ), the horizontal driving manner may be suitably applied in order to reduce light leakage, to improve contrast ratio and aperture ratio of a panel and to lower production costs.
First claim
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The invention claimed is: 1. An array substrate, comprising a gate line and a data line that define a pixel region including a thin film transistor region and a pixel electrode pattern region, wherein in the thin film transistor region a gate electrode, a source electrode, a drain electrode, a gate insulating layer, an active layer and a passivation layer are provided, and a channel part is formed between the source electrode and the drain electrode and recessed to the inner of the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D86/40Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8933472B2 cover?
- An array substrate, which is formed with a gate electrode ( 2 ), a source electrode ( 5 ), a drain electrode ( 6 ), a gate insulating layer ( 3 ), an active layer ( 4 ) and a passivation layer ( 9 ) in a thin film transistor region, and with the gate insulating layer ( 3 ), a pixel electrode ( 7 ), the passivation layer ( 9 ) and a common electrode ( 8 ) in a pixel electrode pattern region, and…
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D86/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).