SiC semiconductor device
US-12080760-B2 · Sep 3, 2024 · US
SiC epitaxial wafer and semiconductor device
US8933464B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933464-B2 |
| Application number | US-201414205792-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 12, 2014 |
| Priority date | Mar 22, 2013 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.
First claim
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What is claimed is: 1. An SiC epitaxial wafer comprising: an SiC substrate; and a p-type first SiC epitaxial layer formed on the SiC substrate, the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a grou…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8933464B2 cover?
- An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D62/8325. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).