Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Semiconductor device structures and methods of forming semiconductor structures
US8933458B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933458-B2 |
| Application number | US-201314048923-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 8, 2013 |
| Priority date | Jun 21, 2005 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
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A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
First claim
Opening claim text (preview).
We claim: 1. A nonplanar transistor, comprising: a semiconductor body disposed on and continuous with a bulk monocrystalline silicon substrate, the semiconductor body comprising inwardly tapered sidewalls that each taper inward from the top of the semiconductor body at an angle of approximately 62.5 degrees, wherein charge migration in the semiconductor body is along a direction perpendicular to the sidewalls; and a gate electrode disposed over the semiconductor body and orthogo…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8933458B2 cover?
- A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the sec…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6212. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).