Phase change memory

Patent metadata

Field	Value
Publication number	US-8933428-B2
Application number	US-201313910956-A
Country	US
Kind code	B2
Filing date	Jun 5, 2013
Priority date	Dec 27, 2010
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

First claim

What is claimed is:

1. A phase change memory comprising:
a peripheral circuit region, comprising:
a peripheral substrate, wherein peripheral shallow trench isolation (STI) units are disposed in the peripheral substrate, and
at least one MOS transistor on the peripheral substrate and between the peripheral STI units, a top surface of the peripheral STI units being coplanar with a bottom surface of the at least one MOS transistor;

a storage region, comprising:
a storage subs…

Assignees

• Semiconductor Mfg Int Corp
• Semiconductor Mfg Int Beijing

Inventors

• Mieno Fumitake
• He Youfeng

Classifications

• H10H29/10 Primary

  Electricity · mapped topic

• H10B63/10

  Electricity · mapped topic

• H01L27/15

  Electricity · mapped topic

• H01L45/1213 Primary

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic