Efficient lock hand-off in a symmetric multiprocessing system

US8930952B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8930952-B2
Application numberUS-201213426293-A
CountryUS
Kind codeB2
Filing dateMar 21, 2012
Priority dateMar 21, 2012
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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Abstract

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Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.

First claim

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We claim: 1. An apparatus, comprising: a plurality of physical processors in a multiprocessor system; a first lock accessible by each processor of the plurality of processors; a computer-readable storage medium; and logic, stored on the computer-readable storage medium, and executed on the plurality of processors, for: acquiring, by a first thread running on a first processor of a plurality of processors, the first lock corresponding to a resource; spinning, by a second…

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What does patent US8930952B2 cover?
Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second proc…
Who is the assignee on this patent?
Michel Dirk, Olszewski Bret R, Vaidyanathan Basu, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F9/526. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).