Processing engine for complex atomic operations
US-9218204-B2 · Dec 22, 2015 · US
US8930952B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930952-B2 |
| Application number | US-201213426293-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 21, 2012 |
| Priority date | Mar 21, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Provided are techniques for providing a first lock, corresponding to a resource, in a memory that is global to a plurality of processor; spinning, by a first thread running on a first processor of the processors, at a low hardware-thread priority on the first lock such that the first processor does not yield processor cycles to a hypervisor; spinning, by a second thread running on a second processor, on a second lock in a memory local to the second processor such that the second processor is configured to yield processor cycles to the hypervisor; acquiring the lock and the corresponding resource by the first thread; and, in response to the acquiring of the lock by the first thread, spinning, by the second thread, at the low hardware-thread priority on the first lock rather than the second lock such that the second processor does not yield processor cycles to the hypervisor.
Opening claim text (preview).
We claim: 1. An apparatus, comprising: a plurality of physical processors in a multiprocessor system; a first lock accessible by each processor of the plurality of processors; a computer-readable storage medium; and logic, stored on the computer-readable storage medium, and executed on the plurality of processors, for: acquiring, by a first thread running on a first processor of a plurality of processors, the first lock corresponding to a resource; spinning, by a second…
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