Non-volatile memory and methods of fabricating the same
US-2024268126-A1 · Aug 8, 2024 · US
Bit-replacement technique for DRAM error correction
US8930779B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930779-B2 |
| Application number | US-201013505449-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 10, 2010 |
| Priority date | Nov 20, 2009 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.
First claim
Opening claim text (preview).
What is claimed is: 1. A dynamic memory device, comprising: a set of dynamic memory cells; a set of replacement dynamic memory cells including: cells to store replacement data bits for predetermined faulty cells in the set of dynamic memory cells; and associated with the cells to store replacement data bits, address cells to store address bits that identify the predetermined faulty cells; and a remapping circuit configured to remap an access to a cell in the set of dynami…
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Physics · mapped topic
- G11C29/50016Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8930779B2 cover?
- The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein …
- Who is the assignee on this patent?
- Ware Frederick A, Tsern Ely, Vogelsang Thomas, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G11C29/50016. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).