Scheduler for multiprocessor system switch with selective pairing

Patent metadata

Field	Value
Publication number	US-8930752-B2
Application number	US-201113027960-A
Country	US
Kind code	B2
Filing date	Feb 15, 2011
Priority date	Feb 15, 2011
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

First claim

Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is:

1. A method for performing operations in a multiprocessing system comprising a plurality of processor cores, said method comprising:
dynamically configuring a selective pairing facility to communicate with at least two processor cores for performing one of: independent parallel operation or highly-reliable fault tolerant operations;
scheduling, by a scheduler device operatively…

Assignees

• Gara Alan
• Gschwind Michael Karl
• Salapura Valentina
• IBM

Inventors

• Gara Alan
• Gschwind Michael Karl
• Salapura Valentina

Classifications

• G06F2201/845

  Physics · mapped topic

• G06F11/165

  Physics · mapped topic

• G06F11/1641 Primary

  Physics · mapped topic