Stack timing adjustment for serial communications
US-2017249278-A1 · Aug 31, 2017 · US
Memory controller
US8930739B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930739-B2 |
| Application number | US-27210008-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 17, 2008 |
| Priority date | Nov 15, 2007 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
Official abstract text for this publication.
A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory controller comprising: a programmable delay unit configured to receive a periodic read-enable signal and to output a delayed periodic read-enable signal having a variable delay time selected in response to a delay-control signal; and a sampling unit configured to output, in synchronization with the delayed periodic read-enable signal, data read out from a memory coupled to the memory controller, wherein the programmable delay unit generates a pl…
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Inventors
Classifications
- G06F13/4239Primary
Physics · mapped topic
- G06F12/00Primary
Physics · mapped topic
- G06F3/061Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8930739B2 cover?
- A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. …
- Who is the assignee on this patent?
- Kim Kwan-Ho, Kim Jong-In, Jang Young-Wook, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F13/4239. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).