Deferred inter-processor interrupts
US-9208113-B2 · Dec 8, 2015 · US
US8930722B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930722-B2 |
| Application number | US-38021009-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2009 |
| Priority date | Feb 29, 2008 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: at least two processing elements having different performance capabilities and power consumption properties, wherein the first one of the at least two processing elements has a first instruction set architecture and the second one of the at least two processing elements has a second instruction set architecture different from the first instruction set architecture; logic to determine whether instructions running on a first one of t…
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