Distribution of tasks among asymmetric processing elements

US8930722B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8930722-B2
Application numberUS-38021009-A
CountryUS
Kind codeB2
Filing dateFeb 25, 2009
Priority dateFeb 29, 2008
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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Abstract

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Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.

First claim

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What is claimed is: 1. An apparatus comprising: at least two processing elements having different performance capabilities and power consumption properties, wherein the first one of the at least two processing elements has a first instruction set architecture and the second one of the at least two processing elements has a second instruction set architecture different from the first instruction set architecture; logic to determine whether instructions running on a first one of t…

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What does patent US8930722B2 cover?
Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
Who is the assignee on this patent?
Sprangle Eric, Carmean Doug, Kumar Rajesh, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F1/3293. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).