Vector processor with vector and element reduction method
US-2024004647-A1 · Jan 4, 2024 · US
US8930682B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930682-B2 |
| Application number | US-96981210-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 16, 2010 |
| Priority date | Dec 16, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
Opening claim text (preview).
What is claimed is: 1. A method comprising: receiving stream data of a first width in an execution unit of a processor from a stream buffer coupled to the execution unit; processing the stream data responsive to an instruction to process data of the first width, wherein the instruction prescribes the first width; determining whether the stream data includes header data, and if so receiving additional stream data from the stream buffer and processing the additional stream data…
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