Processing device and method for managing tasks thereof
US-2024320037-A1 · Sep 26, 2024 · US
Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction
US8930679B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930679-B2 |
| Application number | US-60476709-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 23, 2009 |
| Priority date | May 29, 2009 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.
First claim
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We claim: 1. An out-of-order execution hardware microprocessor for reducing a likelihood of having to replay a load instruction due to a store collision, the hardware microprocessor comprising: a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies a dependee instruction upon which the store instruction depends for its data; and a register alias table…
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- G06F9/3838Primary
Physics · mapped topic
- G06F9/30174Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8930679B2 cover?
- An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction dep…
- Who is the assignee on this patent?
- Day Matthew Daniel, Hooker Rodney E, Via Tech Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3838. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).