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Load page table entry address instruction execution based on an address translation format control field
US8930673B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930673-B2 |
| Application number | US-201314065796-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 29, 2013 |
| Priority date | Jan 11, 2008 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
First claim
Opening claim text (preview).
What is claimed is: 1. A computer program product for performing a load page table entry address (LPTEA) function in a computer system of a machine architecture, said computer system configured to translate a virtual address into a translated address of a block of data in main storage, the computer system having a hierarchy of translation tables for translation of said virtual address, said hierarchy of translation tables comprising a format control translation table containing one…
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- G06F12/1009Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/1027Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8930673B2 cover?
- What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identify…
- Who is the assignee on this patent?
- Greiner Dan F, Heller Lisa C, Osisek Damian L, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1009. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).