Method and apparatus for verifying integrity in memory-disaggregated environment
US-12153525-B2 · Nov 26, 2024 · US
Method and apparatus for realtime detection of heap memory corruption by buffer overruns
US8930657B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930657-B2 |
| Application number | US-201113184999-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 18, 2011 |
| Priority date | Jul 18, 2011 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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- Title
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Abstract
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One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.
First claim
Opening claim text (preview).
What is claimed is: 1. A heap overflow detection system comprising: an arithmetic logic unit configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction; a datapath configured to provide the opcode and the operand to the arithmetic logic unit; and address violation detection logic that determines whether a heap memory access is a violation…
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Physics · mapped topic
- G06F12/1441Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8930657B2 cover?
- One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instr…
- Who is the assignee on this patent?
- Balasubramanian Prakash Kalanjeri, Infineon Technologies Ag
- What technology area does this patent fall under?
- Primary CPC classification G06F12/1441. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).