Memory performance when speculation control is enabled, and instruction therefor
US-2015378915-A1 · Dec 31, 2015 · US
Transactional memory that performs a PPM 32-bit lookup operation
US8930639B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930639-B2 |
| Application number | US-201213675394-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 13, 2012 |
| Priority date | Nov 13, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple prefix values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). Mask values are generated based on the prefix values. The LKV is masked by each mask value thereby generating multiple masked values that are compared to the reference values. Based on the comparison a lookup table generates a selector value that is used to select a result value. The selected result value is then communicated to the processor via the bus.
First claim
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What is claimed is: 1. A method comprising: (a) receiving a lookup command onto a transactional memory, wherein the lookup command includes a memory address, and wherein the transactional memory includes a lookup engine and a memory unit; (b) receiving an input value (IV); (c) using the memory address to read a word out of the memory unit, wherein the word includes a plurality of result values (RVs), a plurality of reference values, and a plurality of prefix values; (d) stor…
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- What does patent US8930639B2 cover?
- A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple prefix values from memory. A selecting circuit within the TM uses a starting bit positio…
- Who is the assignee on this patent?
- Stark Gavin J, Netronome Systems Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/467. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).