Smart memory

Patent metadata

Field	Value
Publication number	US-8930618-B2
Application number	US-201113209794-A
Country	US
Kind code	B2
Filing date	Aug 15, 2011
Priority date	Aug 24, 2010
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

An apparatus comprising a storage device comprising a plurality of memory tiles each comprising a memory block and a processing element, and an interconnection network coupled to the storage device and configured to interconnect the memory tiles, wherein the processing elements are configured to perform at least one packet processing feature, and wherein the interconnection network is configured to promote communication between the memory tiles. Also disclosed is a network component comprising a receiver configured to receive network data, a logic unit configured to convert the network data for suitable deterministic memory caching and processing, a serial input/output (I/O) interface configured to forward the converted network data in a serialized manner, a memory comprising a plurality of memory tiles configured to store and process the converted network data from the serial I/O interface, and a transmitter configured to forward the processed network data from the serial I/O interface.

First claim

What is claimed is:

1. An apparatus comprising:
a memory device comprising a plurality of memory tiles each comprising a memory block and a processing element; and
an interconnection network coupled to the memory device and configured to interconnect the memory tiles,
wherein the memory device is configured to:
allocate a plurality of memory tiles to perform at least network data processing function by employing the processing elements;
group the memory tiles by mapping por…

Assignees

• Kumar Sailesh
• Lynch William
• Futurewei Technologies Inc

Inventors

• Kumar Sailesh
• Lynch William

Classifications

• G06F15/7821 Primary

  Physics · mapped topic

• G06F2213/0038

  Physics · mapped topic

• G06F15/785 Primary

  Physics · mapped topic