Reliable notification of interrupts in a network processor by prioritization and policing of interrupts

US8930604B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8930604-B2
Application numberUS-201213551002-A
CountryUS
Kind codeB2
Filing dateJul 17, 2012
Priority dateJul 17, 2012
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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Abstract

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In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available (i.e., currently unused) capacity of the hardware interrupt buffer is allocated based on those programmed scale factors. If the node determines to handle the detected event using the hardware interrupt buffer, then the node stores a hardware interrupt corresponding to the detected event in the hardware interrupt buffer. Otherwise, the node handles the detected event using a fallback action.

First claim

Opening claim text (preview).

What is claimed is: 1. A node-implemented method for handling events by a node in a data network, the node-implemented method comprising: (a) processing data received at the node to detect an event; (b) classifying the detected event as being one of a plurality of different categories of events; (c) determining, based on the classified category of the detected event, whether to handle the detected event using a hardware interrupt buffer of the node, wherein step (c) comprises:…

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What does patent US8930604B2 cover?
In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of th…
Who is the assignee on this patent?
Pazhayakath Benzeer Bava Arackal, Narayanan Santosh, Lsi Corp
What technology area does this patent fall under?
Primary CPC classification G06F13/24. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).