Processor with hardware supported memory buffer overflow detection
US-11868774-B2 · Jan 9, 2024 · US
Concurrent array-based queue
US8930596B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930596-B2 |
| Application number | US-201213690028-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 30, 2012 |
| Priority date | Nov 30, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
According to one embodiment, a method for implementing an array-based queue in memory of a memory system that includes a controller includes configuring, in the memory, metadata of the array-based queue. The configuring comprises defining, in metadata, an array start location in the memory for the array-based queue, defining, in the metadata, an array size for the array-based queue, defining, in the metadata, a queue top for the array-based queue and defining, in the metadata, a queue bottom for the array-based queue. The method also includes the controller serving a request for an operation on the queue, the request providing the location in the memory of the metadata of the queue.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for implementing an array-based queue in memory of a memory system that includes a controller, the method comprising: configuring, in the memory, metadata of the array-based queue, the configuring comprising: defining, in the metadata, an array start location in the memory for the array-based queue; defining, in the metadata, an array size for the array-based queue; defining, in the metadata, a queue top for the array-based queue; and definin…
Assignees
Inventors
Classifications
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8930596B2 cover?
- According to one embodiment, a method for implementing an array-based queue in memory of a memory system that includes a controller includes configuring, in the memory, metadata of the array-based queue. The configuring comprises defining, in metadata, an array start location in the memory for the array-based queue, defining, in the metadata, an array size for the array-based queue, defining, i…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F12/14. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).