Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US8930593B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930593-B2 |
| Application number | US-27606108-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 21, 2008 |
| Priority date | Nov 26, 2007 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.
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What is claimed is: 1. A storage system comprising: a plurality of storage nodes for storing information wherein said plurality of storage nodes are organized in a chained network and at least one of said plurality of storage nodes includes an upstream communication buffer; and a master controller for controlling flow to said plurality of storage nodes based upon constraints of said upstream communication buffer within said plurality of storage nodes, wherein a communication of…
Physics · mapped topic
Physics · mapped topic
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