Flash memory controller and associated control method
US-2024377989-A1 · Nov 14, 2024 · US
US8930592B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8930592-B2 |
| Application number | US-201313766605-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 13, 2013 |
| Priority date | Feb 13, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Techniques for performing I/O load balancing are provided. In one embodiment, a computer system can receive an I/O request destined for a storage array, where the computer system is communicatively coupled with the storage array via a plurality of paths, and where the plurality of paths include a set of optimized paths and a set of unoptimized paths. The computer system can further determine whether the I/O request can be transmitted to the storage array via either an optimized path or an unoptimized path, or solely via an optimized path. The computer system can then select a path in the plurality of paths based on the determination and transmit the I/O request to the storage array via the selected path.
Opening claim text (preview).
What is claimed is: 1. A method for performing I/O load balancing, the method comprising: receiving, by a computer system, I/O requests destined for a storage array, the computer system being communicatively coupled with the storage array via a plurality of paths, the plurality of paths including a set of optimized paths and a set of unoptimized paths; determining, by the computer system, whether the I/O requests can be load balanced across both the set of optimized paths and th…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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