Decoupled Packet and Data Processing Rates in Switch Devices
US-2016366073-A1 · Dec 15, 2016 · US
US8929381B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8929381-B2 |
| Application number | US-201213567126-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 6, 2012 |
| Priority date | Mar 31, 2004 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.
Opening claim text (preview).
What is claimed is: 1. A method comprising: performing packet processing on a packet including extracting a payload from said packet; using a data movement circuit to place the payload corresponding to said packet into a read buffer substantially simultaneously while performing packet processing and substantially simultaneously with a direct memory access (DMA) operation of the data movement circuit. 2. The method of claim 1 , wherein said performing packe…
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