Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8929144-B2
Application number	US-201313755419-A
Country	US
Kind code	B2
Filing date	Jan 31, 2013
Priority date	Feb 8, 2012
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

According to one embodiment, a control circuit of a memory cell array is configured to write data to a memory cell array by applying a first write pass voltage, which is lower than the program voltage, to a first group of nonselective word lines adjacent to a selective word line. The control circuit is further configured to apply a second write pass voltage, which is higher than the first write pass voltage, to a second group of second nonselective word lines, the second group not including the word lines of the first group.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells connected in series to form a memory string;
a plurality of word lines, each word line connected to a control gate of a respective memory cell in the memory string; and
a control circuit configured to control a data write to the memory cell array, wherein
the control circuit applies:
a program voltage to a selected word line,
a first writ…

Assignees

• Toshiba Kk

Inventors

• Izumi Tatsuo

Classifications

• G11C16/0483

  Physics · mapped topic

• G11C16/0408 Primary

  Physics · mapped topic