Memory device and operation method thereof
US-11862234-B2 · Jan 2, 2024 · US
US8929129B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8929129-B2 |
| Application number | US-201313946458-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 19, 2013 |
| Priority date | Jul 27, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at first node; third and fourth transistors of second conductivity type coupled in series between first and second lines and coupled to each other at second node; power supply node coupled in common to first and second nodes; fifth transistor of first conductivity type coupled between first and second signal lines; and sixth transistor of second conductivity type coupled between first and second signal lines, wherein each of first, second and fifth transistors is configured to receive first control signal at gate electrode thereof, each of the third and fourth transistors is configured to receive second control signal at gate electrode thereof, and sixth transistor is configured to receive third control signal at gate electrode thereof.
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What is claimed is: 1. A device, comprising: first and second signal lines; first and second transistors of a first conductivity type coupled in series between the first and second signal lines and coupled to each other at a first node; third and fourth transistors of a second conductivity type coupled in series between the first and second lines and coupled to each other at a second node; a power supply node coupled in common to the first and second nodes; a fifth transis…
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