System and methods using a multiplexed reference for sense amplifiers
US-9202543-B2 · Dec 1, 2015 · US
Sample and hold buffer
US8929102B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8929102-B2 |
| Application number | US-201213527335-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 19, 2012 |
| Priority date | Jun 19, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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This relates to sampling a feedback signal representative of an output of a power converter. The sampling is performed using a buffer sampling circuit having three sample and hold stages coupled in series to sense and store the feedback signal. The first stage is coupled to sample and hold the feedback signal on a capacitor. If the output diode is conducting, the sampled signal is transferred to the second stage. If the output diode is conducting, the first stage will sample the feedback signal and the sampled signal will be transferred to be sampled and held by the second stage. When the output diode stops conducting, the sampled voltage held by the second stage is transferred to the third stage. The third stage stores the sampled voltage on a capacitor. As such, the controller may sample the feedback signal near the end of the output diode conduction time.
First claim
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What is claimed is: 1. A circuit for sampling a feedback signal representative of an output of a power converter, the circuit comprising: a first sample circuit having an input coupled to receive the feedback signal representative of the output of the power converter, the first sample circuit comprising a first switch coupled to a first capacitor, wherein the first sample circuit is operable to sample the feedback signal and generate a first sample signal based on the sampling of…
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- G11C27/02Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8929102B2 cover?
- This relates to sampling a feedback signal representative of an output of a power converter. The sampling is performed using a buffer sampling circuit having three sample and hold stages coupled in series to sense and store the feedback signal. The first stage is coupled to sample and hold the feedback signal on a capacitor. If the output diode is conducting, the sampled signal is transferred t…
- Who is the assignee on this patent?
- Zhang Guangchao, Power Integrations Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C27/02. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).