Shift register, gate driver on array panel and gate driving method

US8928573B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8928573-B2
Application numberUS-201213806177-A
CountryUS
Kind codeB2
Filing dateNov 20, 2012
Priority dateDec 30, 2011
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The embodiment of the present invention discloses a shift register for reducing the power consumption during driving. The shift register includes a protection circuit, a retaining circuit, an output circuit, a first driving circuit, a second driving circuit, a resetting circuit, a timing control terminal, a first power supply terminal, a second power supply terminal, a third power supply terminal and a fourth power supply terminal. The embodiment of the present invention further discloses a Gate driver On Array (GOA) panel and a method for gate driving.

First claim

Opening claim text (preview).

What is claimed is: 1. A shift register applied to a Gate driver On Array TFT-LCD panel, including a protection circuit for ensuring an output signal of an output circuit to be at a first level signal, a retaining circuit for controlling the protection circuit, an output circuit for outputting a signal, a first driving circuit for driving the output circuit, a second driving circuit for driving the retaining circuit, a resetting circuit for resetting the shift register, a timing co…

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What does patent US8928573B2 cover?
The embodiment of the present invention discloses a shift register for reducing the power consumption during driving. The shift register includes a protection circuit, a retaining circuit, an output circuit, a first driving circuit, a second driving circuit, a resetting circuit, a timing control terminal, a first power supply terminal, a second power supply terminal, a third power supply termin…
Who is the assignee on this patent?
Beijing Boe Optoelectronics
What technology area does this patent fall under?
Primary CPC classification G09G3/3677. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).